Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional charging circuit. This charging circuit 100 generally comprises a high voltage switch Q1 (which is generally a high voltage PMOS transistor) that is controlled by a control signal CNTL so as to provide current to the external capacitor CEXT from a voltage source VSUP1. Typically, the power (PQ1) in the switch Q1 and the time (τ) for charging are as follows:PQ1=VDSQ1*IQ1; and  (1)τ=CEXT*VSUP1/IQ1,  (2)where VDSQ1 is the drain-source voltage of switch Q1 and IQ1 is the current through switch Q1. Thus, as an example, if one were to assume that the external capacitor CEXT is 1 mF with a voltage source VSUP1 of 32V and a current IQ1 of 1.5 A, then the time τ would be 21 ms, and the power PQ1 would be 48 W. Additionally, for this application, the area of switch Q1 associated with an ON resistance of 0.5Ω can have a temperature increase of about 60° C. for 5 W of power PQ1. These high temperatures or hot spots may cause unexpected thermal shutdown or cause damage to the device. Therefore, circuit 100 has an undesirable configuration due to susceptibility to high temperatures.
Turning to FIG. 2A, another conventional charging circuit 200 can be seen. Circuit 200 generally comprises switches Q2-1 to Q2-N that are coupled to in parallel to one another between voltage source VSUP1 and external capacitor CEXT so as to reduce the current load on each of the switches Q2-1 to Q2-N. Each of these switches Q2-1 to Q2-N is coupled to and controlled by a respective high voltage inverter level shifter 202-1 to 202-N (which are each coupled voltage source VSUP2).
Level shifters 202-1 to 202-N (hereinafter referred to a 202) can be seen in greater detail in FIG. 2B. Level shifter 202 generally comprises of a low voltage PMOS transistor Q3, high voltage PMOS transistors Q4 and Q6, high voltage NMOS transistors Q5 and Q7, and inverter 204. When the control signal CNTL is logic low or “0”, transistors Q3 and Q7 are activated (while transistor Q5 is deactivated) so as to deactivate transistor Q6 and couple node N2 to ground. Alternatively, when the control signal CNTL is logic high or “1”, transistors Q3 and Q7 are deactivated (while transistor Q5 is activated) so as to activate transistor Q6 and couple node N2 to the voltage source VSUP2. Additionally, in operation, when control signal CNTL is logic high, transistor Q4 operates to limit the voltage on node N1 to prevent oxide breakdown of transistor Q6 when activated.
As can be easily seen from FIG. 2B, level shifter 202 occupies a considerable amount of area, and with an array of level shifters (as shown in FIG. 2A), the area usage may be prohibitively large. High voltage switch Q1 is used as a “high side device” with a low ON resistance in native mode and re-used as a charging switch in charging mode. Moreover, because switches Q2-1 to Q2-N are activated simultaneously (or nearly simultaneously) in charging mode, there are very tight delay matching requirements that can result in a very challenging layout in native mode of operation. One more thing to consider is, if the delays are not matched, the rise/fall times of the switch may not be optimal. This configuration also needs additional control signals from the digital logic. Thus, circuit 200 is undesirable.
Therefore, there is a need for charging circuitry that does not have the drawbacks of conventional charging circuitry.
Some other conventional circuits are: U.S. Pat. No. 5,909,135; U.S. Pat. No. 6,441,681; U.S. Patent Pre-Grant Publ. No. 2005/0068089; and U.S. Patent Pre-Grant Publ. No. 2009/0085615.